In conventional electroplating methods, copper electrodeposition in the presence of additives can produce void-free plating of submicron features such as vias and trenches in dual-damascene metallization. This approach is conventionally practiced for fabricating interconnects in advanced microprocessors at sub-50 nm technology nodes. However, as interconnects shrink in dimension, scaling the interconnect metallization process to narrower geometries becomes increasingly difficult. For example, physical vapor deposition (PVD) of copper on the cobalt liner can result in undesirable defects such as protrusion, or “overhang,” at the feature opening leading to pinch-off. Furthermore, sidewall step coverage of these small features can also result in sidewall voiding after plating. Such defects can lead to electrical shorts and reliability problems.
The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.